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参数资料
| 型号： | SI5334B-A00122-GM |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 30/34页 |
| 文件大小： | 233K |
| 代理商： | SI5334B-A00122-GM |
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Si5334
Preliminary Rev. 0.16
5
Table 3. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Core Supply Current
IDD
100 MHz on all outputs,
25 MHz refclk
—45
60
mA
Output Buffer Supply Current
IDDOx
LVPECL, 710 MHz
—
30
mA
LVDS, 710 MHz
—
8
mA
HCSL, 250 MHz
2 pF load
——
20
mA
SSTL, 350 MHz
—
19
mA
CMOS, 50 MHz
15 pF load
——
28
mA
CMOS, 200 MHz
2 pF load, 3.3 V VDD0
——
20
mA
CMOS, 200 MHz
2 pF load, 2.5 V
—13
17
mA
CMOS, 200 MHz
2 pF load, 1.8 V
—11
15
mA
HSTL, 350 MHz
—
19
mA
Table 4. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance
Junction to Ambient
JA
Still Air
37
°C/W
Thermal Resistance
Junction to Case
JC
Still Air
25
°C/W
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PLL Acquisition Time
tACQ
——
25
ms
PLL Lock Range
fLOCK
5000
—
ppm
PLL Loop Bandwidth
fBW
—1.6
—
MHz
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Keep MultiSynth output frequency between 5 MHz to Fvco/8.
3. Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.
4. Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5334B-A00122-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334B-A00154-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334B-A00154-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334B-A00156-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334B-A00156-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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