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参数资料
| 型号： | SI5334B-A00122-GM |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 7/34页 |
| 文件大小： | 233K |
| 代理商： | SI5334B-A00122-GM |
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Si5334
Preliminary Rev. 0.16
15
Based
on
this
architecture,
the
output
of
each
MultiSynth can produce any frequency from 5 to Fvco/8
MHz. To support higher frequency operation, the
MultiSynth divider can be bypassed. In bypass mode
integer divide ratios of 4 and 6 are supported, which
allows for output frequencies of Fvco/4 and Fvco/6 MHz
which translates to 367–473.3 MHz and 550–710 MHz
respectively. Because each MultiSynth uses the same
VCO output there are output frequency limitations when
output frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce
Fvco/4 = 562.5 MHz
or
Fvco/6 = 375 MHz.
Only two unique frequencies above Fvco/8 can be
output: Fvco/6 and Fvco/4.
2.5. Output Driver
There are four clock output channels on the Si5334
(CLK0,CLK1,CLK2,CLK3) with two signal outputs per
channel. Each channel may be programmed to be a
differential driver or a dual single ended driver. If a
channel is factory-programmed to be single ended, then
the two outputs for that channel can be factory-
programmed to be in-phase or out-of-phase. Si5334
output drivers can be configured as single ended
CMOS, SSTL, HSTL or differential LVPECL, LVDS, and
HCSL formats.
The supply voltage requirement for each driver format is
selectable as shown in Table 14. All unused clock
output channels must have their respective VDD0x
supply voltage connected to pin 7 and 24 VDD.
Figure 2. Silicon Labs’ MultiSynth Technology
Fractional-N
Divider
Phase
Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
fVCO
fOUT
MultiSynth
Table 14. Output Driver Signal Format Selection
VDD0x
Supply
Voltage
CMOS
SSTL
HSTL
LVPECL
LVDS
HCSL
1.5
X
1.8
X
2.5
X
3.3
X
相关PDF资料 |
PDF描述 |
|---|---|
| SI5334C-A00129-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00153-GM | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00160-GM | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334A-A00102-GM | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334B-A00123-GM | PLL BASED CLOCK DRIVER, QCC24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5334B-A00122-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334B-A00154-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334B-A00154-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334B-A00156-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334B-A00156-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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