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参数资料
| 型号： | SI5338H-A-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 17/44页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN I2C BUS PROG 24QFN |
| 标准包装： | 490 |
| 系列： | MultiSynth™ |
| 类型： | * |
| PLL： | 是 |
| 输入： | CML，HCSL，HSCL，LVDS，LVPECL，晶体 |
| 输出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 350MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
Si5338
24
Rev. 1.3
Figure 13. Output Enable Control Registers
3.8. Power Consumption
The Si5338 Power consumption is a function of
Supply voltage
Frequency of output Clocks
Number of output Clocks
Format of output Clocks
Because of internal voltage regulation, the current from
the core VDD is independent of the VDD voltage and
hence the plot shown in Figure 14 can be used to
estimate the VDD core (pins 7 and 24) current.
The current from the output supply voltages can be
estimated from the values provided in Table 3, “DC
Characteristics,” on page 5. To get the most accurate
value
for
VDD
currents,
the
Si5338-EVB
with
Clockbuilder software should be used. To do this, go to
the
“Power”
tab
of
the
Clockbuilder
and
press
“Measure”. In this manner, a specific configuration can
be implemented on the EVB and the actual current for
each supply voltage measured. When doing this it is
critical that the output drivers have the proper load
impedance for the selected format.
When testing for output driver current with HSTL and
SSTL, it is required to have load circuitry as shown in
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers”. The
Si5338 EVB has layout pads that can be used for this
purpose. When testing for output driver current with
LVPECL the same layout pads can be used to
implement the LVPECL bias resistor of 130
(2.5 V
VDDx) or 200
(3.3 V VDDx). See the schematic in the
Si5338-EVB data sheet and AN408 for additional
information.
230
OEB
0
OEB
1
OEB
2
OEB
3
OEB
All
1
2
3
4
5
6
7
0 = enable
1 = disable
110
0
1
2
3
4
5
6
7
CLK0 OEB
State
114
0
1
2
3
4
5
6
7
CLK1 OEB
State
118
0
1
2
3
4
5
6
7
CLK2 OEB
State
122
0
1
2
3
4
5
6
7
CLK3 OEB
State
00 = disabled tri-state
01 = disabled low
10 = disabled high
11 = always enabled
Bits reserved
Bits used by other functions
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5338H-A-GMR | 功能描述:时钟发生器及支持产品 I2C-Program Clk Gen 0.16-350MHz inc/dec RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5338H-B00191-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00300-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338H-B00300-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00385-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
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