参数资料
型号: SI5338H-A-GM
厂商: Silicon Laboratories Inc
文件页数: 2/44页
文件大小: 0K
描述: IC CLK GEN I2C BUS PROG 24QFN
标准包装: 490
系列: MultiSynth™
类型: *
PLL:
输入: CML,HCSL,HSCL,LVDS,LVPECL,晶体
输出: CMOS,HCSL. HSTL. LVDS. LVPECL. SSTL
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 是/是
频率 - 最大: 350MHz
除法器/乘法器: 是/是
电源电压: 1.71 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 托盘
Si5338
10
Rev. 1.3
CMOS Output
Resistance
—50
SSTL Output
Resistance
—50
HSTL Output
Resistance
—50
CMOS Output Volt-
age8
VOH
4 mA load
VDDO – 0.3
V
VOL
4 mA load
0.3
V
SSTL Output Voltage
VOH
SSTL-3
VDDOx = 2.97 to
3.63 V
0.45xVDDO+0.41
V
VOL
0.45xVDDO
–0.41
V
VOH
SSTL-2
VDDOx = 2.25 to
2.75 V
0.5xVDDO+0.41
V
VOL
0.5xVDDO–
0.41
V
VOH
SSTL-18
VDDOx = 1.71 to
1.98 V
0.5xVDDO+0.34
V
VOL
0.5xVDDO–
0.34
V
HSTL Output Voltage
VOH
VDDO = 1.4 to
1.6 V
0.5xVDDO+0.3
V
VOL
0.5xVDDO –
0.3
V
Duty Cycle5
DC
45
55
%
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Use an external 100
resistor to provide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 18.
7. CML output format requires ac-coupling of the differential outputs to a differential 100
load at the receiver.
8. Includes effect of internal series 22
resistor.
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