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参数资料
| 型号： | SI5975DC-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | MOSFET 2P-CH 12V 3.1A CHIPFET |
| 标准包装： | 3,000 |
| 系列： | TrenchFET® |
| FET 型： | 2 个 P 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 12V |
| 电流 - 连续漏极(Id) @ 25° C： | 3.1A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 86 毫欧 @ 3.1A，4.5V |
| Id 时的 Vgs(th)（最大）： | 450mV @ 1mA |
| 闸电荷(Qg) @ Vgs： | 9nC @ 4.5V |
| 功率 - 最大： | 1.1W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SMD，扁平引线 |
| 供应商设备封装： | 1206-8 ChipFET? |
| 包装： | 带卷 (TR) |
AN812
Vishay Siliconix
Front of Board
ChipFET r
FIGURE 3.
Back of Board
vishay.com
160
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30 _ C/W typical, 40 _ C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package R Q jf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57 _ C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38 _ C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
200
Min. Footprint
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical R Q ja for the dual-channel 1206-8 ChipFET is
90 _ C/W steady state, identical to the SO-8. Maximum ratings
are 110 _ C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
Testing
120
80
40
Dual EVB
1” Square PCB
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of R Q ja for the Dual 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see 185 _ C/W
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
2) The evaluation board with the pad pattern 128 _ C/W
described on Figure 3.
0
10 -5 10 -4 10 -3 10 -2 10 -1 1 10 100 1000
Time (Secs)
FIGURE 4. Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
3) Industry standard 1” square pcb with
maximum copper both sides.
www.vishay.com
2
90 _ C/W
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126) .
Document Number: 71127
12-Dec-03
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| SI5975DC-T1-GE3 | 功能描述:MOSFET 2P-CH 12V 3.1A CHIPFET RoHS:是 类别:分离式半导体产品 >> FET - 阵列 系列:TrenchFET® 产品目录绘图:8-SOIC Mosfet Package 标准包装:1 系列:- FET 型:2 个 N 沟道（双） FET 特点:逻辑电平门 漏极至源极电压(Vdss):60V 电流 - 连续漏极(Id) @ 25° C:3A 开态Rds（最大）@ Id, Vgs @ 25° C:75 毫欧 @ 4.6A，10V Id 时的 Vgs(th)（最大）:3V @ 250µA 闸电荷(Qg) @ Vgs:20nC @ 10V 输入电容 (Ciss) @ Vds:- 功率 - 最大:1.4W 安装类型:表面贴装 封装/外壳:PowerPAK? SO-8 供应商设备封装:PowerPAK? SO-8 包装:Digi-Reel® 产品目录页面:1664 (CN2011-ZH PDF) 其它名称:SI7948DP-T1-GE3DKR |
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| SI-5L1.880G | 制造商:HITACHIMETAL 功能描述: |
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