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| 型号： | SI9976DY-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/8页 |
| 文件大小： | 0K |
| 描述： | IC DRVR MOSF 1/2BRDG N-CH 14SOIC |
| 标准包装： | 550 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 350ns |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 40V |
| 电源电压： | 4.5 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 散装 |
Si9976
Vishay Siliconix
SPECIFICATIONS a
Test Conditions
UnlessOtherwise Specified
Limits
D Suffix ? 40 to 85 _ C
Parameter
Symbol
V+ = 20 to 40 V
T A = Operating Temperature Range
Min c
Typ b
Max c
Unit
Dynamic
Propogation Delay Time
Low to High Level
Propogation Delay Time
High to Low Level
Propogation Delay Time, Low to High Lev-
el, Enable-to-Fault Output
Output Rise Time (G1, G2)
Output Fall Time (G1, G2)
Short Circuit Pulse Width
t PLH
t PHL
t r
t f
t SC
50% IN to V OUT = 5 V, C L = 600 pF
50% IN to FAULT = 2 V, S1 shorted to GND or V+
1 to 10 V, C L = 600 pf
10 to 1 V, C L = 600 pf
50% to 50% of V OUT
G1
G2
G1
G2
350
400
150
50
500
110
50
350
ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
d. To supply the output current of 10 mA on a dc basis, an external 13-V supply must be connected between the CAP pin and the S1 pin with the negative terminal
of the supply connected to S1. This is not needed in an actual application because output currents are supplied by the C BOOT capacitor. Voltage specified with
respect to V+.
e. For testing purposes, the 10-mA load current must be supplied by an external current source to the V DD pin to avoid pulling down the V DD supply.
f. Internally generated voltage for reference only.
g. V CAP = (V+) + (V DD )
TRUTH TABLE
EN
1
1
0
1
1
1
1
X
IN
0
1
X
0
1
1
0
X
Condition
Normal Operation
Normal Operation
Disabled
Load Shorted to V+
Load Shorted to Ground
Undervoltage on C BOOT
Undervoltage on C BOOT
Undervoltage on V DDc
FAULT OUTPUT
0
0
X a
1 b
1 b
0
0
1
G1 OUT
Low
High
Low
Low
Low
Low
Low
Low
G2 OUT
High
Low
Low
Low
Low
Low
High
Low
Notes
a. FAULT output retains previous state until ENABLE rising edge.
b. Latch FAULT condition, reset by ENABLE rising edge.
c. V DD is an internally generated low-voltage supply.
Document Number: 70016
S-40757—Rev. F, 19-Apr-04
www.vishay.com
3
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