参数资料
型号: SI9976DY-E3
厂商: Vishay Siliconix
文件页数: 4/8页
文件大小: 0K
描述: IC DRVR MOSF 1/2BRDG N-CH 14SOIC
标准包装: 550
配置: 半桥
输入类型: 非反相
延迟时间: 350ns
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 40V
电源电压: 4.5 V ~ 16.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 散装
Si9976
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC-14
NC
CAP
V+
V DD
IN
EN
V CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
S1
G1
NC
GND
G2
FAULT
ORDERING INFORMATION
Part Number Temperature Range Package
Si9976DY
Si9976DY-T1 ? 40 to 85 _ C SOIC-14
Si9976DY-T1—E3
Top View
PIN DESCRIPTION
Pin 1
No connection.
Pin 2: CAP
Connection for the positive terminal of the bootstrap capacitor
C BOOT . A 0.01- m F C BOOT capacitor can be used for most
applications.
Pin 3: V+
This is the only external power supply required for the Si9976,
and must be the same supply used to power the half-bridge it
is driving. The Si9976 powers it’s low-voltage logic, low-side
gate driver, and bootstrap/charge pump circuits from
self-contained voltage regulators which require only a
bootstrap capacitor on the CAP pin and a bypass capacitor on
the V DD pin.
No voltage sensing circuitry monitors V+ directly; however, the
low-voltage, internally generated V DD supply and the
bootstrap voltage (which are derived from V+) are directly
protected by undervoltage monitors.
Pin 4: V DD
Connection to the internally generated low-voltage supply
which must be bypassed to ground with a 0.01- m F capacitor.
Pin 5: IN
Logic input. A low level input turns off the high-side half-bridge
MOSFET and, after an internally set dead time, turns the
low-side half-bridge MOSFET on. A high input level has the
opposite effect. The input is compatible with 5-, 12- or 15-V
logic outputs.
Pin 6: EN
Enable input. A low EN input level prevents turn on of either
half-bridge MOSFET. If the Si9976 is internally disabled as a
result of an output short-circuit condition, a low-to-high
transition on EN is required to clear the fault and resume
operation. The input logic levels are the same as IN.
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4
Pin 7: V CC
If the FAULT output is used, the V CC pin must be connected to
the logic supply voltage in order to set the high level of the
FAULT output. If the FAULT output is not used, this pin may be
left open with no effect on internal fault sensing or protection
circuitry.
Pin 8: FAULT
The Fault output is latched high when a short-circuit output
condition is detected. FAULT will return low when the circuit is
reset using the EN pin. The FAULT output also indicates the
status of the undervoltage sense circuit on V DD , however the
fault condition is cleared automatically when the undervoltage
condition clears.
Pin 9: G2
This pin drives the gate of the external low-side power
transistor.
Pin 10: GND
The ground return for V+, logic reference, and connection for
source of external low-side power transistor.
Pin 11
No connection.
Pin 12: G1
This pin drives the gate of the external high side power
transistor.
Pin 13: S1
Connection for the source of the external high-side power
transistor, the drain of the external low-side power transistor,
the negative terminal of the bootstrap capacitor, and the
system load. The voltage on this pin is sensed by the circuitry
that monitors the load for shorts.
Pin 14
No connection.
Document Number: 70016
S-40757—Rev. F, 19-Apr-04
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