参数资料
型号: SIC769ACD-T1-GE3
厂商: Vishay Siliconix
文件页数: 8/19页
文件大小: 0K
描述: IC CTLR PFC STAGE PPAK MLP66-40
标准包装: 1
系列: DrMOS
类型: 高端/低端驱动器
输入类型: PWM
输出数: 1
电流 - 输出 / 通道: 35A
电源电压: 3 V ~ 16 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-PowerWFQFN
供应商设备封装: PowerPAK? MLP66-40
包装: 标准包装
其它名称: SIC769ACD-T1-GE3DKR
SiC769ACD
Vishay Siliconix
PIN CONFIGURATION
SMOD 1
30 V S W H
V CI N 2
V DR V 3
BOOT 4
C G N D 5
GH 6
PHASE 7
V I N 8
V I N 9
V I N 10
A G N D
P1
V I N
P2
V S W H
P3
29 V S W H
2 8 P G N D
27 P G N D
26 P G N D
25 P G N D
24 P G N D
23 P G N D
22 P G N D
21 P G N D
Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View
PIN DESCRIPTION
Pin Number
1
2
3
4
5, 37, PAD1
6
7
8 to 14, PAD2
15, 29 to 35,
PAD3
16 to 28
36
38
39
40
www.vishay.com
8
Symbol
SMOD
V CIN
V DRV
BOOT
C GND
GH
PHASE
V IN
VSWH
P GND
GL
THDN
DSBL#
PWM
Description
Disable low side gate operation. Active low.
This will be the bias supply input for control IC (5 V).
IC bias supply and gate drive supply voltage (5 V).
High side driver bootstrap voltage pin for external bootstrap capacitor.
Control signal ground. It should be connected to P GND externally. All pins internally connected.
Gate signal output pin for high side MOSFET. Pin for monitoring.
Return pin for the HS bootstrap capacitor. Connect a 0.1 μF ceramic capacitor from this pin to the boot pin (4).
Input voltage for power stage. It is the drain of the high-side MOSFET.
It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected
to an output inductor. All pins internally connected.
Power ground.
Gate signal output pin for low side MOSFET. Pin for monitoring.
Thermal shutdown open drain output. Use a 10K pull up resistor to V CIN .
Disable pin. Active low.
PWM input logic signal. Compatible with Tristate controller function.
Document Number: 65708
S10-0113-Rev. B, 18-Jan-10
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