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参数资料
| 型号： | SIW3500GIG3 |
| 厂商： | RF MICRO DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA96 |
| 封装： | 6 X 6 MM, GREEN, VFBGA-96 |
| 文件页数： | 27/28页 |
| 文件大小： | 795K |
| 代理商： | SIW3500GIG3 |
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Preliminary
8 of 28
SiW3500
60 0066 R00JIrf SiW3500 UltimateBlue SoC DS
UART Interface (Power from VDD_P_ALT)
UART_RXD
CMOS input
G3
24
UART receive data.
UART_TXD
CMOS output
L4
29
UART transmit data.
UART_CTS
CMOS input
H2
18
UART flow control clear to send.
UART_RTS
CMOS output
H1
16
UART flow control ready to send.
EXT_WAKE
CMOS input
C5
13
Wake up signal from host.
External Memory Interface (power from VDD_P)
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
CMOS output
E11
J11
L5
F11
B8
K6
L7
A10
H11
A11
B11
K9
K7
C10
K10
D10
L11
62
51
32
60
78
36
38
73
54
72
71
44
39
69
46
66
47
Address lines.
Note: A[17] and A[16] can be used to support an optional
external serial EEPROM when using the internal ROM in
place of the external Flash memory.
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CMOS bi-directional
A9
C9
B10
E10
K5
G11
G10
H9
K4
J9
K8
J6
J5
F9
J4
H10
75
74
70
63
33
57
56
55
30
52
43
37
34
61
31
53
Data lines.
Note: Connect D[9] to D[10] to use internal ROM.
OE_N
CMOS output
L10
45
Output enable for external memory (active low).
WE_N/EEPROM_WP
CMOS output
A8
79
Write enable for external memory (active low).
FCS_N
CMOS output
J10
50
Chip select for external memory (active low).
Power and Ground
VBATT_ANA
Power
D3
6
Positive supply to internal analog voltage regulator.
VBATT_DIG
Power
L9
42
Positive supply to internal digital voltage regulator.
VCC_OUT
Power
D1
5
Regulated output from internal analog voltage regulator.
VDD_P
Power
D11
K11
65
48
Positive supply for external memory interface and some digital
I/Os.
VDD_C
Power
C11
L8
68
41
Positive supply for digital circuitry or output of internal digital
voltage.
Name
Pad Type
Ball
Bump
See Note 1
Description
Table 1. SiW3500 SoC Pin List (Continued)
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