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参数资料
| 型号： | SJ80C32XXX-12SV |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封装： | JLCC-44 |
| 文件页数： | 32/109页 |
| 文件大小： | 10824K |
| 代理商： | SJ80C32XXX-12SV |
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277
7593L–AVR–09/12
AT90USB64/128
3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
23.18.2
USB device endpoint registers
7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
2-0 - EPNUM2:0 Endpoint Number bits
Load by software to select the number of the endpoint which shall be accessed by the CPU. See
Section 23.5, page 263 for more details.
EPNUM = 111b is forbidden.
7 - Reserved
The value read from these bits is always 0. Do not set these bits.
6-0 - EPRST6:0 - Endpoint FIFO Reset bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 23.3, page 262 for more information
Then, clear by software to complete the reset operation and start using the endpoint.
7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
5 - STALLRQ - STALL Request Handshake bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 23.11, page 266 for more details.
4 - STALLRQC - STALL Request Clear Handshake bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 23.11, page 266 for more details.
Bit
7
654
321
0
-
EPNUM2:0
UENUM
Read/write
RRR
RR
R/W
Initial value
0
000
0
Bit
7
654
321
0
-
EPRST6
EPRST5
EPRST4
EPRST3
EPRST2
EPRST1
EPRST0
UERST
Read/write
R
R/W
Initial value
0
000
0
Bit
7
6
543
2
1
0
-
STALLRQ
STALLRQC
RSTDT
-
EPEN
UECONX
Read/write
R
W
R
R/W
Initial value
0
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