- 您现在的位置：买卖IC网 > PDF目录25623 > SJ80C32XXX-12SV (ATMEL CORP) 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 PDF资料下载
参数资料
| 型号： | SJ80C32XXX-12SV |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封装： | JLCC-44 |
| 文件页数： | 50/109页 |
| 文件大小： | 10824K |
| 代理商： | SJ80C32XXX-12SV |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页
30
AT32UC3A
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
9.4.2
Exceptions and interrupt requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus
Error) can not be masked. When an event is accepted, hardware automatically sets the
mask bits corresponding to all sources with equal or lower priority. This inhibits accep-
tance of other events of the same or lower priority, except for the critical events listed
above. Software may choose to clear some or all of these bits after saving the neces-
sary state if other priority schemes are desired. It is the event source’s responsability to
ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2 or INT3, regis-
ters R8-R12 and LR are also automatically stored to stack. Storing the Status Register
ensures that the core is returned to the previous execution mode when the current
event handling is completed. When exceptions occur, both the EM and GM bits are set,
and the application may manually enable nested exceptions if desired by clearing the
appropriate bit. Each exception handler has a dedicated handler address, and this
address uniquely identifies the exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown inTable 9-4, is
loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2 or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
9.4.3
Supervisor calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
9.4.4
Debug requests
The AVR32 architecture defines a dedicated debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
32058K
AVR32-01/12
相关PDF资料 |
PDF描述 |
|---|---|
| S80C52EXXX-20SHXXX:D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| SCC9521002-01C | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| S80C52XXX-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| S80C32E-40SHXXX:RD | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 |
| S80C52TXXX-12 | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SJ81200 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SJ83100 | 制造商:ON Semiconductor 功能描述:SJ83100 - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SJ83180 | 制造商:ON Semiconductor 功能描述:NPN TO-3 METAL PWR TRANSISTOR - Trays 制造商:Rochester Electronics LLC 功能描述:NPN TO-3 METAL PWR TRANSISTOR - Bulk |
| SJ84140 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SJ-870 | 制造商:NEL 制造商全称:Nel Frequency Controls,inc 功能描述:CRYSTAL CLOCK OSCILLATORS |
发布紧急采购，3分钟左右您将得到回复。