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| 型号： | SJ80C32XXX-12SV |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封装： | JLCC-44 |
| 文件页数： | 88/109页 |
| 文件大小： | 10824K |
| 代理商： | SJ80C32XXX-12SV |
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65
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the
CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value
of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF)
and wrap around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare
Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1). The OC0A value will not be visible on
the port pin unless the data direction for the pin is set to output. When OCR0A is set to zero (0x00) the waveform
generated will have a maximum frequency of fclk_I/O/2. The waveform frequency is defined by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from
MAX to 0x00.
11.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts
from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and OCR0A when
WGM0[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare
Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can
be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast
PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on page 66.
The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
Compare Matches between OCR0x and TCNT0.
f
OCnx
f
clk_I/O
2 N
1
OCRnA
+
---------------------------------------------------
=
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