参数资料
型号: SL28540ALC
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: OTHER CLOCK GENERATOR, QCC56
封装: 8 X 8 MM, LEAD FREE, QFN-56
文件页数: 19/25页
文件大小: 267K
代理商: SL28540ALC
SL28540
Rev 1.2, September 15, 2008
Page 3 of 25
21
VSS_IO
GND
Ground for outputs.
22
VDD_PLL3
PWR
3.3V Power supply for PLL3.
23
SRCT1 / LCDT_100
O, DIF True 100 MHz differential serial reference clock output/True 100 MHz LCD
video clock output
24
SRCC1 / LCDC_100
O, DIF Complementary 100 MHz differential serial reference clock output/Comple-
mentary 100 MHz LCD video clock output
25
VSS_PLL3
GND
Ground for PLL3.
26
VDD_PLL3_IO
PWR
3.3V-1.05V power supply for outputs.
27
SRCT2
O, DIF True 100 MHz differential serial reference clock output.
28
SRCC2
O, DIF Complementary 100 MHz differential serial reference clock output.
29
VSS_SRC
GND
Ground for outputs.
30
SRCT3 / CR#_C
I/O,
DIF
True 100 MHz differential serial reference clock output /3.3V Clock Request
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
31
SRCC3 / CR#_D
I/O,
DIF
Complementary 100 MHz differential serial reference clock output/3.3V Clock
Request #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
32
VDD_SRC_IO
PWR
3.3V-1.05V Power supply for outputs.
33
SRCT4
O, DIF True 100 MHz differential serial reference clocks.
34
SRCC4
O, DIF Complementary 100 MHz differential serial reference clocks.
35
SRCT11
O, DIF True 100 MHz differential serial reference clocks.
36
SRCC11
O, DIF Complementary 100 MHz differential serial reference clocks.
37
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 12
for more information.
38
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 12
for more information.
39
VDD_SRC
PWR
3.3V power supply for SRC PLL.
40
VSS_SRC
GND
Ground for outputs.
41
SRCC7/ CR#_E
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
42
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
43
VDD_SRC_IO
PWR
3.3V-1.05V Power supply for outputs.
44
SRCC8 / CPUC2_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
45
SRCT8 / CPUT2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
46
NC
No connect.
Pin Definitions (continued)
Pin No.
Name
Type
Description
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