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参数资料
| 型号： | SL28540ALC |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC56 |
| 封装： | 8 X 8 MM, LEAD FREE, QFN-56 |
| 文件页数： | 20/25页 |
| 文件大小： | 267K |
| 代理商： | SL28540ALC |
SL28540
Rev 1.2, September 15, 2008
Page 4 of 25
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
47
VDD_CPU_IO
PWR
3.3V-1.05V Power supply for outputs.
48
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
49
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
50
VSS_CPU
GND
Ground for outputs.
51
CPUC0
O, DIF Complement differential CPU clock outputs.
52
CPUT0
O, DIF True differential CPU clock outputs.
53
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
54
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
55
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
56
VSS_REF
GND
Ground for outputs.
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
REF
DOT96
USB
1
0
1
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
166 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
Pin Definitions (continued)
Pin No.
Name
Type
Description
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
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| SL28540ALCT | 功能描述:时钟发生器及支持产品 Low Power for Intel Mobile RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BQCR | 功能描述:时钟发生器及支持产品 Montevina, Atom RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BQCRT | 功能描述:时钟发生器及支持产品 Montevina, Atom RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZC | 功能描述:时钟发生器及支持产品 Montevina RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZC-2 | 功能描述:时钟发生器及支持产品 Montevina, Atom RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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