参数资料
型号: SL28540ALC
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: OTHER CLOCK GENERATOR, QCC56
封装: 8 X 8 MM, LEAD FREE, QFN-56
文件页数: 6/25页
文件大小: 267K
代理商: SL28540ALC
SL28540
Rev 1.2, September 15, 2008
Page 14 of 25
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 7. CPU_STP# Deassertion Waveform
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running
CPUT(Free Running
PD#
1.8 ms
CPU_STOP#
DOT96C
DOT96T
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
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