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参数资料
| 型号： | SL38160ZI-XXXT |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封装： | ROHS COMPLIANT, TSSOP-16 |
| 文件页数： | 10/11页 |
| 文件大小： | 171K |
| 代理商： | SL38160ZI-XXXT |
Rev 1.1, January 5, 2009
Page 8 of 11
SL38160
Power supply Ramp
Time
tPSR
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
-
12
ms
PLL Lock Time
tPLL
Time from VDD reaching minimum
specified value to valid output
frequencies at all outputs
-
7.5
9.0
ms
Spread Percent Range
SPR-1
Center Spread
+/-0.125
-
+/-2.5
%
Spread Percent Range
SPR-2
Down Spread
-5.0
-
-0.25
%
Modulation Frequency
FMOD
Programmable, 31.5 kHz standard
25
31.5
120
kHz
VCXO Pull Range
ΔFVCXO VCXO Crystal Pull Range
+/-110
+/-120
-
ppm
Clock Output
Frequency Selection Pins
Selected Number of Frequencies
TBD
Table 1. Frequency Selection Options for Clock Outputs
Programmable Output Clock (CLKOUT) Rise and Fall Times
The output clock rise and fall times (tr/tf) of each clock output can be programmed independently to match drive level
to load impedance.
Programming
Code
VDDO=3.3V
CL=15pF
VDDO=2.5V
CL=15pF
Unit
000
4.00
4.80
ns
001
2.00
2.60
ns
010
1.40
1.80
ns
011
1.10
1.40
ns
100
0.85
1.10
ns
101
0.70
0.90
ns
110
0.55
0.70
ns
Table 2. Programmable CLKOUT Rise and Fall Times
Notes:
1. All typical values are at respective nominal VDD values.
2. The worst case rise and fall times variations are +/- 20% for C-Grade and +/-30% for I-grade.
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