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参数资料
| 型号： | SL38160ZI-XXXT |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封装： | ROHS COMPLIANT, TSSOP-16 |
| 文件页数： | 6/11页 |
| 文件大小： | 171K |
| 代理商： | SL38160ZI-XXXT |
Rev 1.1, January 5, 2009
Page 4 of 11
SL38160
General Description
The primary source of EMI from digital circuits is the
system clock and all the other synchronous clock and
control signals derived from the system clock. The well
know techniques of filtering (suppression) and shielding
(containment), while effective, can cost money, board
space and longer development time.
A more effective and efficient technique to reduce EMI is
Spread Spectrum Clock Generator (SSCG) technique to
control and reduce EMI emissions. Instead of using
constant
clock
frequency,
the
SSCG
technique
modulates
the
system
clock
with
much
smaller
frequency, to reduce EMI emissions at its source: The
System Clock.
The SL38160 is a Spread Spectrum Clock Generator
(SSCG)
IC
used
for
the
purpose
of
reducing
electromagnetic interference (EMI) found in today’s high-
speed digital electronic systems.
The devices use a SpectraLinear proprietary phase-
locked loop (PLL) and Spread Spectrum Technologies
(SST) to synthesize and modulate (spread) the system
clock such that the energy is spread out over a wider
bandwidth. This reduces the peak radiated emissions at
the fundamental and the harmonics.
This reduction in
radiated energy can significantly reduce the cost of
complying with regulatory agency requirements and
improve time-to-market without degrading system perfor-
mance.
The SL38160 is available in 16-pin TSSOP packages
with a Commercial Temperature range of 0 to 70
°C and
Industrial Temperature range of –40 to 85°C.
Refer to 28-pin TSSOP package version of SL38160,
called
SL38000, for up to nine programmable outputs
and additional control functions
Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz for
crystals in XO Mode. If an external driven clock is used,
the input frequency range is from 3 to 166 MHz.
In VCXO mode pullable crystal range is 13 to 30MHz.
Output Frequency Range
The five clock outputs can be programmed as CLKOUT,
SSCLK
or
REFCLK.
If
VDD=VDDO=3.3V,
output
frequency range is 3 to 200MHz with CL=15pF-max. If
VDD=3.3V and VDDO=2.5V, output frequency range for
CLKOUT-2/3/4/5 is 3 to 166MHz. REFCLK is the
buffered output of the oscillator and can be programmed
from 0.25 to 48MHz in XO mode and 25 to 30MHz in
VCXO mode.
Programmable Output Rise and Fall Times
The each output clock drivers can be programmed
independently
for
different
frequencies
and
load
conditions to improve signal integrity and EMI radiation
levels. Refer Table 1 for available seven rise and fall time
program values.
Programmable CL (Crystal Load) in XO Mode
The SL38160 provides programmable on-chip capacitors
at XIN/CLKIN (Pin-1) and XOUT (Pin-16). The resolution
of this programmable capacitor is 6-bits with LSB value of
0.5pF. When all bits are off the pin capacitance is
CXIN=CXOUT =8.5pF (minimum value). When all bits are
on the pin capacitance at these pins is
CXIN=CXOUT=40pF (maximum value).
The values of CXIN and CXOUT based on the CL (Crystal
Load Capacitor) can be calculated as:
CXIN=CXOUT=2CL-CPCB.
In addition, if an external clock is used, the capacitance at
Pin-1 (CLKIN) can programmed to control the edge rate of
this input clock, providing additional EMI control.
Programmable Modulation Frequency
The Spread Spectrum Clock (SSC) modulation default
value is 31.5 kHz. The higher values of 60, 90 and 120
kHz can also be programmed. Less than 30 kHz
modulation frequency is not recommended to stay out of
the range audio frequency bandwidth.
Spread Percent (%)
The spread percent (%) value is programmable from +/-
0.25% to +/-2.5% (center spread) or -0.5% to -5.0%
(down spread) for all input and SSCLK frequencies. It is
possible to program smaller or larger values of spread
percent for certain frequencies. Contact SLI if these non-
standard spread percent values are required.
VDD/VDDO
SL38160 provides two separate VDDO1 and VDDO-2
power pins to power CLKOUT-1/-2/-3 and CLKOUT-3/-4
clock output drivers respectively. VDD pin powers digital
core, PLLs and crystal oscillator in both XO and VCXO
modes. VDD and VDD0 can be 2.5V to 3.3V +/-10%
where VDD
≥VDDO.
XO/VCXO Modes
SL38160 can be programmed to operate in XO or VCXO
mode. If XO mode is selected external crystal can be 8 to
48MHz. Refer to Table 3 for recommended XO crystal
specifications.
In VCXO mode 25 to 30 MHz pullable crystal must be
used. Refer to Table 4 for pullable VCXO crystal
specifications.
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