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参数资料
| 型号： | SL811HS |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | SL811HS Embedded USB Host/Slave Controller(SL811HS嵌入式USB主/从控制器) |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 2/32页 |
| 文件大小： | 455K |
| 代理商： | SL811HS |
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SL811HS
Document 38-08008 Rev. *B
Page 10 of 32
3.1.3.6
Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh]
This register has two modes: a Read from this register indicates the current SL811HS silicon revision.
Writing to this register will set up auto generation of SOF to all connected peripherals. This counter is based on the 12-MHz clock
and is not dependent on the crystal frequency. To set up a 1-ms timer interval, the software must set up both SOF counter registers
to the proper values.
Example: To set up SOF for 1-ms interval, SOF counter register 0Eh should be set to E0h.
3.1.3.7
SOF Counter HIGH/Control Register 2 [Address = 0Fh]
When read, this register will return the value of the SOF counter divided by 64. The software should use this register to determine
the available bandwidth in the current frame before initiating any USB transfer. In this way, the user will be able to avoid babble
conditions on the USB. For example, to determine the available bandwidth left in a frame:
Maximum number of clock ticks in 1-ms time frame is 12000 (1 count per 12-MHz clock period, or approximately 84 ns.) The
value read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12-MHz period.
Value of register 0FH
Available bit times left are between
BBH
12000 bits to 11968 (187 × 64) bits
BAH
11968 bits to 11904 (186 × 64) bits
Note: Any Write to the 0Fh register will clear the internal frame counter. Register 0Fh must be written at least once after power-
up. The internal frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which
is used to track the frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave
every millisecond in a SOF packet.
6
Device Detect/Resume Device Detect/Resume Interrupt.
Bit 6 is shared between Device Detection status and Resume detection interrupt. When
bit-6 of register 05h is set to one, this bit will be the Resume detection Interrupt bit.
Otherwise, this bit is used to indicate the presence of a Device, “1” = device “Not
present” and “0” = device “Present.” In this mode this bit should be checked along with
bit 5 to determine whether a device has been inserted or removed.
5
Insert/Remove
Device Insert/Remove Detection.
Bit 5 is provided to support USB cable Insertion/Removal for the SL811HS in Host
Mode. This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE
to SE0 (device removed) occurs on the bus.
4
SOF timer
1 = Interrupt on SOF Timer.
3Reserved
0
2Reserved
0
1
USB-B
USB-B Done Interrupt. (See description in Interrupt Enable Register [address 06h]).
0
USB-A
USB-A Done Interrupt. (See description in Interrupt Enable Register [address 06h]).
Table 3-15. Hardware Revision when READ [Address 0Eh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hardware Revision
Reserved
Bit Position
Bit Name
Function
7-4
Hardware Revision
SL11H Read = 0H, SL811HS rev1.2 Read = 1H, SL811HS rev1.5 Read = 2.
3-2
Reserved
Read will be zero.
1-0
Reserved
Reserved for slave.
Table 3-16. SOF Counter LOW Address when WRITTEN [Address 0Eh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOF7
SOF6
SOF5
SOF4
SOF3
SOF2
SOF1
SOF0
Bit Position
Bit Name
Function
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SL811HS_07 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Embedded USB Host/Slave Controller |
| SL811HS_11 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Embedded USB Host/Slave Controller |
| SL811HS-DK | 制造商:Cypress Semiconductor 功能描述:Embedded USB Host/Slave Controller 28-Pin PLCC |
| SL811HS-JCT | 制造商:Cypress Semiconductor 功能描述: |
| SL811HST | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Embedded USB Host/Slave Controller |
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