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参数资料
型号： SM320C6414DGADW60
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 64-BIT, 75 MHz, OTHER DSP, CPGA570
封装： 33 X 33 MM, CERAMIC, FCPGA-570
文件页数： 27/134页
文件大小： 1997K
代理商： SM320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
122
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
NO.
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
4
tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12*
2 12P*
ns
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
4*
5 + 24P*
ns
*This parameter is not production tested.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
NO.
PARAMETER
MASTER§
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high
T 2*
T + 3*
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
H 2*
H + 3*
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
2*
4*
12P + 4*
20P + 17*
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
H 2*
H + 3*
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
4P + 3*
12P + 17*
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2*
16P + 17*
ns
*This parameter is not production tested.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
8
7
6
2
1
CLKX
FSX
DX
DR
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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