- 您现在的位置：买卖IC网 > PDF目录98084 > SM320C6414DGADW60 (TEXAS INSTRUMENTS INC) 64-BIT, 75 MHz, OTHER DSP, CPGA570 PDF资料下载
参数资料
| 型号： | SM320C6414DGADW60 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| 封装： | 33 X 33 MM, CERAMIC, FCPGA-570 |
| 文件页数： | 8/134页 |
| 文件大小： | 1997K |
| 代理商： | SM320C6414DGADW60 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
105
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING
timing requirements for reset (see Figure 37)
NO.
MIN
MAX
UNIT
1
tw(RST)
Width of the RESET pulse (PLL stable)
10P*
ns
1
tw(RST)
Width of the RESET pulse (PLL needs to sync up)§
250*
s
16
tsu(boot)
Setup time, boot configuration bits valid before RESET high
4P*
ns
17
th(boot)
Hold time, boot configuration bits valid after RESET high
4P*
ns
*This parameter is not production tested.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable.
§ This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock
PLL circuit. The PLL, however, may need up to 250
s to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
EMIFB address pins BEA[20:13, 11, 7] are the boot configuration pins during device reset.
switching characteristics over recommended operating conditions during reset#|| (see Figure 37)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(RSTL-ECKI)
Delay time, RESET low to ECLKIN synchronized internally
2E*
3P + 20E*
ns
3
td(RSTH-ECKI)
Delay time, RESET high to ECLKIN synchronized internally
2E*
8P + 20E*
ns
4
td(RSTL-ECKO1HZ)
Delay time, RESET low to ECLKOUT1 high impedance
2E*
ns
5
td(RSTH-ECKO1V)
Delay time, RESET high to ECLKOUT1 valid
8P + 20E*
ns
6
td(RSTL-EMIFZHZ)
Delay time, RESET low to EMIF Z high impedance
2E*
3P + 4E*
ns
7
td(RSTH-EMIFZV)
Delay time, RESET high to EMIF Z valid
16E*
8P + 20E*
ns
8
td(RSTL-EMIFHIV)
Delay time, RESET low to EMIF high group invalid
2E*
ns
9
td(RSTH-EMIFHV)
Delay time, RESET high to EMIF high group valid
8P + 20E*
ns
10
td(RSTL-EMIFLIV)
Delay time, RESET low to EMIF low group invalid
2E*
ns
11
td(RSTH-EMIFLV)
Delay time, RESET high to EMIF low group valid
8P + 20E*
ns
12
td(RSTL-LOWIV)
Delay time, RESET low to low group invalid
0*
ns
13
td(RSTH-LOWV)
Delay time, RESET high to low group valid
11P*
ns
14
td(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
0*
ns
15
td(RSTH-ZV)
Delay time, RESET high to Z group valid
2P*
8P*
ns
*This parameter is not production tested.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
# E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
|| EMIF Z group consists of:
AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,
AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of:
ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)
is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO
pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section
of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,
DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,
TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,
GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,
and URCLAV.
相关PDF资料 |
PDF描述 |
|---|---|
| SM320C6416DGADW60 | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| SMJ320C6701GLPW16 | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| SMJ34010-50FDM | GRAPHICS PROCESSOR, CQCC68 |
| SMJ34010-40GBM | GRAPHICS PROCESSOR, CPGA68 |
| SMJ34010FDM | GRAPHICS PROCESSOR, CQCC68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6414-EP | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| SM320C6415DGADW60 | 制造商:Texas Instruments 功能描述:DSP Fixed-Point 32-Bit 600MHz 4800MIPS 570-Pin FCPGA Tray |
| SM320C6416DGADW60 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXD-POINT DIGITAL SIGNAL PROCESSORS |
| SM320C6424GDUQ6EP | 功能描述:数字信号处理器和控制器 - DSP, DSC EP Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| SM320C6455BGTZEP | 功能描述:数字信号处理器和控制器 - DSP, DSC Enh Product Fixed- Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。