参数资料
型号: SM320C6414DGADW60
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 64-BIT, 75 MHz, OTHER DSP, CPGA570
封装: 33 X 33 MM, CERAMIC, FCPGA-570
文件页数: 73/134页
文件大小: 1997K
代理商: SM320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
HAS/PPAR§
N7
I/O/Z
Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR§
N9
I/O/Z
Host chip select (I) [default] or PCI parity error (I/O/Z)
HDS1/PSERR§
R5
I/O/Z
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
HDS2/PCBE1§
P6
I/O/Z
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
HRDY/PIRDY§
N4
I/O/Z
Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
HD31/AD31§
J4
HD30/AD30§
K7
HD29/AD29§
J5
HD28/AD28§
K4
HD27/AD27§
K5
HD26/AD26§
L6
HD25/AD25§
L8
HD24/AD24§
J6
HD23/AD23§
L5
HD22/AD22§
M5
Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415 and C6416]
HD21/AD21§
M6
As HPI data bus (PCI_EN pin = 0)
HD20/AD20§
M8
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
HD19/AD19§
L4
Used for transfer of data, address, and control
Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/pulldown
resistor on the HD5 pin:
HD18/AD18§
M4
resistor on the HD5 pin:
HD17/AD17§
M9
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
HD16/AD16§
M7
I/O/Z
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
HD15/AD15§
P8
I/O/Z
reserved pins in the high-impedance state.)
HD14/AD14§
R6
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD13/AD13§
R4
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD12/AD12§
P7
As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only]
HD11/AD11§
R7
As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only]
Used for transfer of data and address
HD10/AD10§
T5
Used for transfer of data and address
The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are
HD9/AD9§
T4
The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are
standalone peripheral functions, not MUXed.
HD8/AD8§
P9
standalone peripheral functions, not MUXed.
HD7/AD7§
T6
HD6/AD6§
R8
HD5/AD5§
U4
HD4/AD4§
U5
HD3/AD3§
T7
HD2/AD2§
U6
HD1/AD1§
V4
HD0/AD0§
V5
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
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