- 您现在的位置：买卖IC网 > PDF目录98083 > SM320C6701GJCA16EP (TEXAS INSTRUMENTS INC) 32-BIT, 166.67 MHz, OTHER DSP, PBGA352 PDF资料下载
参数资料
| 型号： | SM320C6701GJCA16EP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 166.67 MHz, OTHER DSP, PBGA352 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件页数： | 17/62页 |
| 文件大小： | 894K |
| 代理商： | SM320C6701GJCA16EP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
clock PLL
All of the internal C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise
and fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
Table 3. CLKOUT1 Frequency Ranges
PLLFREQ3
(A9)
PLLFREQ2
(D11)
PLLFREQ1
(B10)
CLKOUT1 Frequency Range
(MHz)
0
50140
0
1
65167
0
1
0
130167
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain
the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example,
for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value
of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
Table 4. C6701 PLL Component Selection Table
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(
)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(
s)
x4
12.541.7
50167
2583.5
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
s, the maximum value may be as long as 250 s.
相关PDF资料 |
PDF描述 |
|---|---|
| SM320C6701GLPW16 | 32-BIT, 167 MHz, OTHER DSP, CBGA429 |
| SM320C6701GLPS14 | 32-BIT, 140 MHz, OTHER DSP, CBGA429 |
| SM320C80GFM40 | 64-BIT, 80 MHz, OTHER DSP, CPGA305 |
| SM320F2812HFGM | 16-BIT, 150 MHz, OTHER DSP, CQFP172 |
| SM320MCM41DHFHM40 | 32-BIT, 40 MHz, OTHER DSP, CQFP352 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6701GLPS16 | 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays |
| SM320C6701GLPW14 | 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP |
| SM320C6701S14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701S16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701W14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
发布紧急采购，3分钟左右您将得到回复。