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参数资料
| 型号： | SM320C6701GJCA16EP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 166.67 MHz, OTHER DSP, PBGA352 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件页数： | 44/62页 |
| 文件大小： | 894K |
| 代理商： | SM320C6701GJCA16EP |
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SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP (see Figure 31)
NO.
PARAMETER
C6701-120
C6701-167
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
15
ns
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P§
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C 1#
C + 1#
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
4
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
4
5
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
3
16
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int
3
2
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
CLKX ext
2
9
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX int
2
4
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX ext
3
16
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid.
FSX int
2
4
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid.
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX ext
2
10
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),
whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the
McBSP communicates to is a slave.
# C = H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.
相关PDF资料 |
PDF描述 |
|---|---|
| SM320C6701GLPW16 | 32-BIT, 167 MHz, OTHER DSP, CBGA429 |
| SM320C6701GLPS14 | 32-BIT, 140 MHz, OTHER DSP, CBGA429 |
| SM320C80GFM40 | 64-BIT, 80 MHz, OTHER DSP, CPGA305 |
| SM320F2812HFGM | 16-BIT, 150 MHz, OTHER DSP, CQFP172 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6701GLPS16 | 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays |
| SM320C6701GLPW14 | 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP |
| SM320C6701S14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701S16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701W14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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