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参数资料
| 型号： | SM320C6701GJCA16EP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 166.67 MHz, OTHER DSP, PBGA352 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件页数： | 43/62页 |
| 文件大小： | 894K |
| 代理商： | SM320C6701GJCA16EP |
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SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP (see Figure 31)
NO.
C6701-120
C6701-167
UNIT
NO.
MIN
MAX
UNIT
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P§
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P 1
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
13
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
4
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
7
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
4
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
10
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
1
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
4
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
4
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
13
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
4
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
7
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
§ The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),
whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the
McBSP communicates to is a slave.
The minimum CLKR/X pulse duration is either (P 1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use
9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P 1) = 11.5 ns as the minimum CLKR/X pulse
duration.
相关PDF资料 |
PDF描述 |
|---|---|
| SM320C6701GLPW16 | 32-BIT, 167 MHz, OTHER DSP, CBGA429 |
| SM320C6701GLPS14 | 32-BIT, 140 MHz, OTHER DSP, CBGA429 |
| SM320C80GFM40 | 64-BIT, 80 MHz, OTHER DSP, CPGA305 |
| SM320F2812HFGM | 16-BIT, 150 MHz, OTHER DSP, CQFP172 |
| SM320MCM41DHFHM40 | 32-BIT, 40 MHz, OTHER DSP, CQFP352 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6701GLPS16 | 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays |
| SM320C6701GLPW14 | 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP |
| SM320C6701S14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701S16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701W14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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