参数资料
型号: SM320C6701GJCA16EP
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 32-BIT, 166.67 MHz, OTHER DSP, PBGA352
封装: 35 X 35 MM, PLASTIC, BGA-352
文件页数: 18/62页
文件大小: 894K
代理商: SM320C6701GJCA16EP
SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
clock PLL (continued)
Available Multiply Factors
CLKMODE1
CLKMODE0
PLL Multiply
Factors
CPU Clock
Frequency
f(CPUCLOCK)
0
x1(BYPASS)
1 x f(CLKIN)
0
1
Reserved
1
0
Reserved
1
x4
4 x f(CLKIN)
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000
DSP device as possible. For
the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers,
switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
CLKMODE0
CLKMODE1
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to C6701
CPU
CLOCK
PLLF
1
0
3.3V
(see Table 3)
PLLFREQ1
PLLFREQ2
PLLFREQ3
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
CLKMODE0
CLKMODE1
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to C6701
CPU
CLOCK
C1
R1
3.3V
10
mF
0.1
mF
PLLF
EMI
Filter
C3
C4
1
0
(see Table 3)
PLLFREQ1
PLLFREQ2
PLLFREQ3
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