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| 型号： | SN54LVTH182646A |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT Scan Test Device With 18-Bit Transceivers and Registers(3.3V ABT 扫描检测装置(18位收发器和寄存器)) |
| 中文描述： | 的3.3V ABT生根粉扫描测试设备与18位收发器和寄存器（3.3 ABT生根粉扫描检测装置（18位收发器和寄存器）） |
| 文件页数： | 16/36页 |
| 文件大小： | 829K |
| 代理商： | SN54LVTH182646A |
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SN54LVTH18646A, SN54LVTH182646A, SN74LVTH18646A, SN74LVTH182646A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS311D – MARCH 1994 – REVISED JUNE 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/36-bit mode (PRPG)
X10
Parallel-signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 51–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 51–48 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are only valid when both bytes of the device are operating in one
direction of data flow (that is, 1OEA
≠
1OEB and 2OEA
≠
2OEB) and in the same direction of data flow (that is,
1OEA
=
2OEA and 1OEB
=
2OEB). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
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