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| 型号： | SN54LVTH18516 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| 中文描述： | 的3.3V ABT生根粉扫描测试设备与18位通用总线收发器（3.3VABT扫描测试装置（18位通用总线收发器）） |
| 文件页数： | 15/36页 |
| 文件大小： | 769K |
| 代理商： | SN54LVTH18516 |
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SN54LVTH18516, SN54LVTH182516, SN74LVTH18516, SN74LVTH182516
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS672B – AUGUST 1996 – REVISED JUNE 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
bypass scan
This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the
normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Std 1149.1a-1993 HIGHZ instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a
modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins
remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Std 1149.1a-1993 CLAMP instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for
pins in the output mode is applied to the device I/O pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device
I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data
appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the
test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to be
executed.
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相关PDF资料 |
PDF描述 |
|---|---|
| SN74LVTH18516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| SN54LVTH182516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| SN74LVTH182516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(18位通用总线收发器)) |
| SN54LVTH18640 | 3.3-V ABT Scan Test Device With 18-Bit Inverting Bus Transceivers(3.3V ABT 扫描检测装置(18位反相总线收发器)) |
| SN54LVTH182640 | 3.3-V ABT Scan Test Device With 18-Bit Inverting Bus Transceivers(3.3V ABT 扫描检测装置(18位反相总线收发器)) |
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