参数资料
型号: SN54LVTH18516
厂商: Texas Instruments, Inc.
英文描述: 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
中文描述: 的3.3V ABT生根粉扫描测试设备与18位通用总线收发器(3.3VABT扫描测试装置(18位通用总线收发器))
文件页数: 17/36页
文件大小: 769K
代理商: SN54LVTH18516
SN54LVTH18516, SN54LVTH182516, SN74LVTH18516, SN74LVTH182516
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS672B – AUGUST 1996 – REVISED JUNE 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 6 and 7 illustrate the 36-bit linear-feedback shift-register algorithms through which
the patterns are generated. An initial seed value should be scanned into the BSR prior to performing this
operation. A seed value of all zeroes will not produce additional patterns.
=
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
B9-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
A8-I/O
A9-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A17-I/O
A18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B18-I/O
Figure 6. 36-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
P
相关PDF资料
PDF描述
SN74LVTH18516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN54LVTH182516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN74LVTH182516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(18位通用总线收发器))
SN54LVTH18640 3.3-V ABT Scan Test Device With 18-Bit Inverting Bus Transceivers(3.3V ABT 扫描检测装置(18位反相总线收发器))
SN54LVTH182640 3.3-V ABT Scan Test Device With 18-Bit Inverting Bus Transceivers(3.3V ABT 扫描检测装置(18位反相总线收发器))
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