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| 型号： | SN65LVDTS33D |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-SPEED DIFFERENTIAL RECEIVERS |
| 中文描述： | 高速差分接收器 |
| 文件页数： | 1/23页 |
| 文件大小： | 504K |
| 代理商： | SN65LVDTS33D |
www.ti.com
FEATURES
400-Mbps Signaling Rate
(1)
and 200-Mxfr/s
Data Transfer Rate
Operates With a Single 3.3-V Supply
-4 V to 5 V Common-Mode Input Voltage
Range
Differential Input Thresholds <±50 mV With 50
mV of Hysteresis Over Entire Common-Mode
Input Voltage Range
Integrated 110-
Line Termination Resistors
On LVDT Products
TSSOP Packaging (33 Only)
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output
With No Input
Bus-Pin ESD Protection Exceeds 15 kV HBM
Input Remains High-Impedance on Power
Down
TTL Inputs Are 5 V Tolerant
Pin-Compatible With the AM26LS32,
SN65LVDS32B, μA9637, SN65LVDS9637B
DESCRIPTION
This family of four LVDS data line receivers offers the
widest common-mode input voltage range in the
industry. These receivers provide an input voltage
range specification compatible with a 5-V PECL
signal as well as an overall increased ground-noise
tolerance. They are in industry standard footprints
with integrated termination as an option.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
V
CC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
8
7
6
5
V
CC
1Y
2Y
GND
1A
1B
2A
2B
D OR PW PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
SN65LVDS33D, SN65LVDT33D
SN65LVDS33PW, SN65LVDT33PW
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
logic diagram (positive logic)
SN65LVDT33 ONLY
1A
1B
2A
2B
1Y
2Y
SN65LVDT34 ONLY
logic diagram (positive logic)
SN65LVDS34D, SN65LVDT34D
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL RECEIVERS
The high-speed switching of LVDS signals usually
necessitates the use of a line impedance matching
resistor
at
the
receiving-end
transmission
media.
The
receivers
eliminates
this
integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop or
other termination circuits.
of
the
cable
series
resistor
or
of
by
SN65LVDT
external
(1)
The signalling rate of a line, is the number of voltage transitions
that are made per second expressed in the units bps (bits per
second).
Precise
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds
are still no more than ±50 mV over the full input
common-mode voltage range.
control
of
the
differential
input
voltage
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2001–2004, Texas Instruments Incorporated
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