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参数资料
| 型号： | SN65LVDTS33D |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-SPEED DIFFERENTIAL RECEIVERS |
| 中文描述： | 高速差分接收器 |
| 文件页数： | 13/23页 |
| 文件大小： | 504K |
| 代理商： | SN65LVDTS33D |
www.ti.com
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at
www.ti.com
for
more information.
ACTIVE FAILSAFE FEATURE
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the
limitations seen in present solutions. A detailed theory of operation is presented in application note
The Active
Failsafe Feature of the SN65LVDS32B,
(
SLLA082A
).
_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
B
R
ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
For more application guidelines, see the following documents:
Low-Voltage Differential Signalling Design Notes
(
SLLA014
)
Interface Circuits for TIA/EIA-644
(LVDS) (
SLLA038
)
Reducing EMI With LVDS
(
SLLA030
)
Slew Rate Control of LVDS Circuits
(
SLLA034
)
Using an LVDS Receiver With RS-422 Data
(
SLLA031
)
Evaluating the LVDS EVM
(
SLLA033
)
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and it
detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Figure 13. Receiver With Active Failsafe
13
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| SN65LVEL11D | 功能描述:时钟缓冲器 3.3V PECL 1:2 Fanout Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| SN65LVEL11DGK | 功能描述:时钟缓冲器 3.3V PECL 1:2 Fanout Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| SN65LVEL11DGKR | 功能描述:时钟缓冲器 3.3V PECL 1:2 Fanout Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| SN65LVEL11DR | 功能描述:时钟缓冲器 3.3V PECL 1:2 Fanout Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| SN65LVELT22D | 功能描述:转换 - 电压电平 3.3V Dual LVTTL to Diff LVPECL Trans RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
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