- 您现在的位置：买卖IC网 > PDF目录98091 > SN74ABT18504PMRG4 (TEXAS INSTRUMENTS INC) ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 PDF资料下载
参数资料
| 型号： | SN74ABT18504PMRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| 封装： | GREEN, PLASTIC, LQFP-64 |
| 文件页数： | 31/32页 |
| 文件大小： | 505K |
| 代理商： | SN74ABT18504PMRG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
state diagram description (continued)
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states used to end a data register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance
state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state provides the capability of suspending and resuming data register scan
operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK following entry to the Update-DR state.
Capture-IR
When an instruction register scan is selected, the TAP controller must pass through the Capture-IR state. In the
Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the
rising edge of TCK upon which the TAP controller exits the Capture-IR state.
For the
′ABT18504, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states used to end an instruction register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance
state.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74ABT18640DGGR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74ABT18640DLR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74ABT2240ADWRG4 | ABT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
| SN74ABT2240APWE4 | ABT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
| SN74ABT2240ADBRG4 | ABT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74ABT18640 | 制造商:TI 制造商全称:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS |
| SN74ABT18640DGG | 制造商:TI 制造商全称:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS |
| SN74ABT18640DGGR | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18640DL | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18640DLG4 | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
发布紧急采购，3分钟左右您将得到回复。