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参数资料
| 型号： | SN74ABT18504PMRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| 封装： | GREEN, PLASTIC, LQFP-64 |
| 文件页数： | 32/32页 |
| 文件大小： | 505K |
| 代理商： | SN74ABT18504PMRG4 |
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SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
state diagram description (continued)
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely.
The Pause-IR state provides the capability of suspending and resuming instruction register scan operations
without loss of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR
state.
register overview
With the exception of the bypass and device identification registers, any test register can be thought of as a serial
shift register with a shadow latch on each bit. The bypass and device identification registers differ in that they
contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and is used to tell the device what instruction is to be executed.
Information contained in the instruction includes the mode of operation (either normal mode, in which the device
performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the
test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path
during data register scans, and the source of data to be captured into the selected data register during
Capture-DR.
Table 4 lists the instructions supported by the
′ABT18504. The even-parity feature specified for SCOPE
devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are
defined for SCOPE
devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value will be
shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the
value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is
updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is
reset to the binary value 10000001, which selects the IDCODE instruction.
The instruction register order of scan is illustrated in Figure 2.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDO
TDI
Bit 7
Parity
(MSB)
Bit 0
(LSB)
Figure 2. Instruction Register Order of Scan
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74ABT18640 | 制造商:TI 制造商全称:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS |
| SN74ABT18640DGG | 制造商:TI 制造商全称:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS |
| SN74ABT18640DGGR | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18640DL | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18640DLG4 | 功能描述:特定功能逻辑 Device w/18-Bit Inv Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
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