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| 型号： | SN74V3660-15PEU |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 的3.3V的CMOS先入先出存储器 |
| 文件页数： | 12/50页 |
| 文件大小： | 729K |
| 代理商： | SN74V3660-15PEU |
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
empty flag/output ready (EF/OR)
EF/OR is a dual-purpose pin. In the standard mode, the EF function is selected. When the FIFO is empty, EF
goes low, inhibiting further read operations. When EF is high, the FIFO is not empty.
See Figure 8 for timing information.
In FWFT mode, the OR function is selected. OR goes low at the same time the first word written to an empty
FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition that shifts the last word
from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with REN = low). The previous
data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes low
again.
See Figure 10 for timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered
output.
programmable almost-full flag (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In standard mode, if no reads are performed
after reset (MRS), PAF goes low after (D
–
m) words are written to the FIFO. The PAF goes low after (1024
–
m)
writes for the SN74V3640, (2048
–
m) writes for the SN74V3650, (4096
–
m) writes for the SN74V3660,
(8192
–
m) writes for the SN74V3670, (16384
–
m) writes for the SN74V3680, and (32768
–
m) writes for the
SN74V3690. The offset m is the full offset value. The default setting for this value is shown in Table 2.
In FWFT mode, PAF goes low after (1025
–
m) writes for the SN74V3640, (2049
–
m) writes for the SN74V3650,
(4097
–
m) writes for the SN74V3660, (8193
–
m) writes for the SN74V3670, (16385
–
m) writes for the
SN74V3680, and (32769
–
m) writes for the SN74V3690. The offset m is the full offset value. The default setting
for this value is shown in Table 2.
See Figure 18 for timing information.
If the asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK.
PAF is reset to high on the low-to-high transition of RCLK. If the synchronous PAF configuration is selected, PAF
is updated on the rising edge of WCLK.
See Figure 20 for timing information.
programmable almost-empty flag (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In standard mode, PAE goes low when there
are n words, or fewer, in the FIFO. The offset n is the empty offset value. The default setting for this value is
shown in Table 2.
In FWFT mode, PAE goes low when there are n + 1 words, or fewer, in the FIFO. The default setting for this
value is shown in Table 2.
See Figure 19 for timing information.
If the asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of RCLK.
PAE is reset to high on the low-to-high transition of WCLK. If the synchronous PAE configuration is selected,
PAE is updated on the rising edge of RCLK.
See Figure 21 for timing information.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V3670-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3690-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN75108AN | DUAL LINE RECEIVERS |
| SN55107AFK | DUAL LINE RECEIVERS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V3660-6PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-7PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3670-10PEU | 功能描述:先进先出 8192 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3670-15PEU | 功能描述:先进先出 8192 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3670-6PEU | 功能描述:先进先出 8192 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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