MOTOROLA
MC68HC16Z1
100
MC68HC16Z1TS/D
RASP[1:0] — RAM Array Space Field
This field limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 operates in supervisor mode only, RASP1 has no effect.
RAMTST — RAM Test Register
$YFFB02
RAMTST is for factory test only. Reads of this register return zeros and writes have no effect.
*ADDR[23:20] is at the same logic level as ADDR19 during internal CPU master operation. ADDR[23:20] must
match ADDR19 for the chip select to be active.
RAMBAH and RAMBAL specify an SRAM base address in the system memory map. They can only be
written while the SRAM is in low-power mode (RAMMCR STOP = 1, the default out of reset) and the
base address lock is disabled (RAMMCR RLCK = 0, the default out of reset). This prevents accidental
remapping of the array. Because the CPU16 drives ADDR[23:20] with the value of ADDR19, the value
in the ADDR[23:20] fields must match the value in the ADDR19 field for the array to be accessible.
6.3 SRAM Operation
There are five operating modes.
The RAM module is in normal mode when powered by VDD. The array can be accessed by byte, word,
or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus
cycle or two system clocks. A long word or misaligned word access requires two bus cycles.
Standby mode is intended to preserve RAM contents when VDD is removed. SRAM contents are main-
tained by a power source connected to the VSTBY pin. The standby voltage is referred to as VSB. Cir-
cuitry within the SRAM module switches to the higher of VDD or VSB with no loss of data. When SRAM
is powered from the VSTBY pin, access to the array is not guaranteed. If standby operation is not desired,
connect the VSTBY pin to VSS.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous
reset occurs while a byte or word SRAM access is in progress, the access will be completed. If reset
occurs during the first word access of a long-word operation, only the first word access will be complet-
ed. If reset occurs during the second word access of a long word operation, the entire access will be
completed. Data being read from or written to the RAM may be corrupted by asynchronous reset.
Test mode is used for factory testing of the RAM array.
Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM array is dis-
abled which, if necessary, allows external logic to decode SRAM addresses but all data is retained. If
VDD falls below VSB, internal circuitry switches to VSB, as in standby mode. Exit the stop mode by clear-
ing the STOP bit.
RASP
Space
X0
Program and Data
X1
Program
RAMBAH — Array Base Address Register High
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
ADDR
23*
ADDR
22*
ADDR
21*
ADDR
20*
ADDR
19
ADDR
18
ADDR
17
ADDR
16
RESET:
0
RAMBAL — Array Base Address Register Low
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RESET:
0