参数资料
型号: SPC5200CVR400
厂商: Freescale Semiconductor
文件页数: 72/80页
文件大小: 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
标准包装: 40
系列: MPC52xx
处理器类型: 32-位 MPC52xx PowerPC
速度: 400MHz
电压: 1.5V
安装类型: 表面贴装
封装/外壳: 272-BBGA
供应商设备封装: 272-PBGA(27x27)
包装: 托盘
MPC5200 Data Sheet, Rev. 4
System Design Information
Freescale Semiconductor
74
5.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash
Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to
ensure that they contain stable values when no agent is actively driving the bus. This includes
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and
PCI_REQ.
5.3.3
Pull-up/Pull-down Requirements for MEM_MDQS pins
(SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down
resistors in SDRAM mode.
5.4
JTAG
The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also
provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The
COP Interface provides access to the MPC5200's imbedded Freescale (formerly Motorola) MPC603e
G2_LE processor. This interface provides a means for executing test routines and for performing software
development & debug functions.
5.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional
in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC
architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted
during power-on reset.
5.4.1.1
JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The
JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting
JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
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