SPC560P50x, SPC560P44x
flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer
hits allow no-wait responses. Normal flash memory array accesses are registered and are
forwarded to the system bus on the following cycle, incurring 3 wait-states.
The flash memory module provides the following features:
●
Up to 576 KB flash memory
–
8 blocks (32KB + 2×16KB + 32KB + 32KB + 3x128KB) Code Flash
–
4 blocks (16KB + 16KB + 16KB + 16KB) Data Flash
–
Full Read While Write capability between Code and Data Flash
●
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
●
Typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page
buffer miss at 60 MHz
●
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
●
Hardware and software configurable read and write access protections on a per-master
basis.
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Configurable access timing allowing use in a wide range of system frequencies.
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Multiple-mapping support and mapping-based block access timing (0–31 additional
cycles) allowing use for emulation of other memory types.
●
Software programmable block program/erase restriction control.
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Erase of selected block(s)
●
Read page size of 128 bits (4 words)
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64-bit ECC with single-bit correction, double-bit detection for data integrity
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Embedded hardware program and erase algorithm
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Erase suspend, program suspend and erase-suspended program
●
Censorship protection scheme to prevent flash memory content visibility
●
Hardware support for EEPROM emulation
3.3.5
On-chip SRAM with ECC
The SPC560Px SRAM module provides a general-purpose memory of up to 40 KB in total.
ECC handling is done on a 32-bit boundary and is completely software compatible with
SPC560Px family devices with an e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
●
Supports read/write accesses mapped to the SRAM memory from any master
●
40 KB general purpose RAM
●
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
●
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8-
and 16-bit writes if back to back with a read to same memory block
3.3.6
Interrupt Controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems.