![](http://datasheet.mmic.net.cn/140000/SPC560P44L5CEFB_datasheet_5015175/SPC560P44L5CEFB_9.png)
SPC560P50x, SPC560P44x
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
The crossbar provides the following features:
●
4 master ports:
–
e200z0 core complex Instruction port
–
e200z0 core complex Load/Store Data port
–eDMA
–FlexRay
●
3 slave ports:
–
Flash memory (code flash and data flash)
–SRAM
–
Peripheral bridge
●
32-bit internal address, 32-bit internal data paths
●
Fixed Priority Arbitration based on Port Master
●
Temporary dynamic priority elevation of masters
3.3.3
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.
The eDMA module provides the following features:
●
16 channels support independent 8, 16 or 32 bit single value or block transfers
●
Supports variable sized queues and circular queues
●
Source and destination address registers are independently configured to post-
increment or remain constant
●
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
●
Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
●
DMA transfers possible between system memories, DSPI’s, ADC, FlexPWM, eTimer
and CTU
●
Programmable DMA Channel Mux allows assignment of any DMA source to any
available DMA channel with up to a total of 30 potential request sources.
●
eDMA abort operation through software
3.3.4
On-chip flash memory with ECC
The SPC560Px provides up to 576 KB of programmable, non-volatile, flash memory. The
non-volatile memory (NVM) can be used for instruction and/or data storage. The flash
memory module interfaces the system bus to a dedicated flash memory array controller. It
supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to