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参数资料
| 型号： | SPC5634MF0MLQA8 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 80 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, 1.40 HEIGHT, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 43/122页 |
| 文件大小： | 1173K |
| 代理商： | SPC5634MF0MLQA8 |
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Overview
MPC5634M Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
27
–
Detects ‘equal’ and ‘not equal’
–
Byte, half word, word (naturally aligned)
NOTE
This feature is imprecise due to CPU pipelining.
— Subset of Power Architecture Book E software debug facilities with OnCE block (Nexus class 1 features)
eTPU development support features
— IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
— Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)
Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses
for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid
prototyping for powertrain automotive development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O port
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
1.3.20.2
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant
with the IEEE 1149.1-2001 standard and supports the following features:
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
— ACCESS_AUX_TAP_ONCE
— ACCESS_AUX_TAP_eTPU
— ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode
— Bypass register
— Boundary scan register
— Device identification register
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Censorship Inhibit Register
— 64-bit Censorship password register
— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash
shadow row, Censorship is disabled until the next system reset
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SPC5634MF0MLUA4 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5634MF0MLUA6 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5634MF0MLUA8 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High performance e200z335 core processor |
| SPC5634MF0MMGA4 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5634MF0MMGA6 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
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