参数资料
型号: SST25WF040-40-5I-SAF-T
厂商: Microchip Technology
文件页数: 21/36页
文件大小: 0K
描述: IC FLASH SER 4MB 40MHZ SPI 8SOIC
标准包装: 2,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 4M (512K x 8)
速度: 40MHz
接口: SPI 串行
电源电压: 1.65 V ~ 1.95 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling
any new Write operations from occurring. The WRDI instruction will not terminate any programming
operation in progress. Any program operation in progress may continue up to T BP after executing the
WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 19 for
the WRDI instruction sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
04
MSB
HIGH IMPEDANCE
1328 Fx19.0
Figure 19: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Write-Status-Register instruction must be
executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-
step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP
(software data protection) command structure which prevents any accidental alteration of the status
register values. CE# must be driven low before the EWSR instruction is entered and must be driven
high before the EWSR instruction is executed. See Figure 20 for EWSR instruction followed by WRSR
instruction.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but
cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and
the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or
WP# pin is driven high (V IH ) prior to the low-to-high transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a sin-
?2011 Silicon Storage Technology, Inc.
21
DS25016A
06/11
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