参数资料
型号: SST89E54RD2A-40-C-NJE
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封装: ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44
文件页数: 66/78页
文件大小: 1671K
代理商: SST89E54RD2A-40-C-NJE
Data Sheet
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
69
2008 Silicon Storage Technology, Inc.
S71339-02-000
02/08
FIGURE
14-1: IDD vs. Frequency for 5V SST89E5xRD2A/RDA
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15mA
Maximum IOL per 8-bit port:26mA
Maximum IOL total for all outputs:71mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise
due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification
when the address bits are stabilizing.
5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches
its maximum value when VIN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
50
40
30
20
10
0
51015
20
2530
35
40
I DD
(mA)
Internal Clock Frequency (MHz)
1339 F34.0
Maximum Idle IDD
Typical Idle IDD
Maximum Active IDD
Typical Active IDD
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