- 您现在的位置：买卖IC网 > PDF目录1969 > SSTUB32S869BHLFT (IDT, Integrated Device Technology Inc)IC REGIST BUFF 14BIT DDR2 150BGA PDF资料下载
参数资料
| 型号： | SSTUB32S869BHLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/17页 |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 2,000 |
| 类型： | 缓冲器 |
| Tx/Rx类型： | LVCMOS |
| 延迟时间： | 3.0ns |
| 电容 - 输入： | 3.5pF |
| 电源电压： | 1.7 V ~ 1.9 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 150-TFBGA |
| 供应商设备封装： | 150-CABGA（8x13） |
| 包装： | 带卷 (TR) |
11
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VIK
II = -18mA
-1.2
IOH = -100A
1.7V
VDDQ - 0.2
IOH = -16mA
1.7V
1.2
IOL = 100A
1.7V
0.2
IOL = 16mA
1.7V
0.5
II
All Inputs
VI = VDD or GND
1.9V
±5
A
Standby (Static)
RESET# = GND
0.2
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
TBD
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK# switching
50% duty cycle.
TBD
/clock
MHz
Dynamic Operating
(per each data input)
RESET# = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
TBD
A/ clock
MHz/data
Input capacitance,
Dn, PAR_IN inputs
VI = VREF ± 250 mV
2.5
3.5
pF
Input capacitance,
DCS#n
2
3pF
Input capacitance,
CK and CK# inputs
2
3pF
Input capacitance,
RESET# input
VI = VDD or GND
Note 2
pF
Data Inputs
2.5
3.5
CLK and CLK#
2
3
RESET#
2.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
CONDITIONS
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
1.8V
1.9V
1.8V
VI = VREF ± 250 mV
VICR = 0.9V; VI(PP) = 600 mV
2 - The vendor must supply this value for full device description.
Ci
VOH
VOL
IDD
IDDD
IO = 0
pF
V
VI = VDDQ or GND
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
相关PDF资料 |
PDF描述 |
|---|---|
| ST16C1450CJ28-F | IC UART FIFO 1B 28PLCC |
| ST16C2450CJ44-F | IC DUART 44PLCC |
| ST16C2550CJ44-F | IC DUART FIFO 16B 44PLCC |
| ST16C2552IJ44TR-F | IC UART FIFO 16B DUAL 44PLCC |
| ST16C450CJ44-F | IC UART SINGLE 44PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTUBF32866AHLF | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96CABGA - Trays |
| SSTUBF32866AHLFT | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96LFBGA - Tape and Reel |
| SSTUBF32866BHLF | 制造商:Integrated Device Technology Inc 功能描述:DDR 800 REGISTER. BGA 96 - Bulk |
| SSTUBF32866BHLF8 | 制造商:Integrated Device Technology Inc 功能描述:DDR 800 REGISTER. BGA 96 - Tape and Reel |
| SSTUBV32866BHLFT/M | 制造商:Integrated Device Technology Inc 功能描述:SSTUBV32866BHLFT/M - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。