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参数资料
| 型号： | SSTUB32S869BHLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/17页 |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 2,000 |
| 类型： | 缓冲器 |
| Tx/Rx类型： | LVCMOS |
| 延迟时间： | 3.0ns |
| 电容 - 输入： | 3.5pF |
| 电源电压： | 1.7 V ~ 1.9 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 150-TFBGA |
| 供应商设备封装： | 150-CABGA（8x13） |
| 包装： | 带卷 (TR) |
15
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Error output load circuit and voltage measurement information (VDD =1.8 V± 0.1V)
All input pulses are supplied by generators having the following characteristics: PRR10 MHz;
Zo =50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET#
input
Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
inputs
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
inputs
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 1 k
002aaa500
VCC/2
tPLH
VCC
0 V
0.15 V
VOH
0 V
Output
Waveform 2
LVCMOS
RESET
Input
002aaa501
VICR
tHL
VCC/2
VCC
VOL
Timing
Inputs
Output
Waveform 1
VI(PP)
VICR
002aaa502
VICR
tLH
VOH
0 V
Timing
Inputs
Output
Waveform 2
VI(PP)
VICR
0.15 V
002aaa503
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