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参数资料
| 型号： | SSTUB32S869BHLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 2,000 |
| 类型： | 缓冲器 |
| Tx/Rx类型： | LVCMOS |
| 延迟时间： | 3.0ns |
| 电容 - 输入： | 3.5pF |
| 电源电压： | 1.7 V ~ 1.9 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 150-TFBGA |
| 供应商设备封装： | 150-CABGA（8x13） |
| 包装： | 带卷 (TR) |
13
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
Figure 6 — Parameter M easurement I nfor mation (VDD = 1.8 V ± 0.1 V)
RL = 1000
CL = 30 pF
(see Note 1)
LOAD CIRCUIT
tw
VICR
Inpu t
VIH
VIL
VOLTAGE WAVEFORMS – PULSE DURATION
VREF
Inpu t
tsu
th
VID
VICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
VICR
VID
VICR
Output
VOL
VOH
VTT
tPHL
tPLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
tRPHL
VOL
VOH
VIL
VIH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VDD/2
VTT
tact
tinact
LVCMOS
Input
RST#
VOLTAGE AND CURRENT WAVEFORMS
IDD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIMES
0 V
VDD
Test Point
VDD/2
LVCMOS
Inp ut
RESET#
TL=350ps, 50
DUT
CK#
Out
TL
td = 350ps
=50
CK Inputs
VID
CK
RL = 100
CK
Test Point
RL = 1000
VDD
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