- 您现在的位置：买卖IC网 > PDF目录98143 > SSTUG32865ET/S (NXP SEMICONDUCTORS) SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 PDF资料下载
参数资料
| 型号： | SSTUG32865ET/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封装： | 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160 |
| 文件页数： | 9/28页 |
| 文件大小： | 154K |
| 代理商： | SSTUG32865ET/S |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
SSTUG32865_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 August 2007
17 of 28
NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3]
Data and clock inputs must be held at valid levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 11.
Timing requirements
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclock
clock frequency
-
550
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
[1][2] --10
ns
tINACT
differential inputs inactive time
[1][3] --15
ns
tsu
set-up time
Chip Select; DCS0, DCS1
valid before clock
switching
0.6
-
ns
Data; Dn valid before
clock switching
0.5
-
ns
PARIN; PARIN before CK
and CK
0.5
-
ns
th
hold time
input to remain valid after
clock switching
0.4
-
ns
PARIN after CK and CK
0.4
-
ns
Table 12.
Switching characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
550
-
MHz
tPDM
peak propagation delay
CK and CK to output
[1] 1.0
-
1.4
ns
tLH
LOW to HIGH delay time
CK and CK to PTYERR
1.2
-
3
ns
tHL
HIGH to LOW delay time
CK and CK to PTYERR
1
-
3
ns
tPLH
LOW-to-HIGH propagation delay
from RESET to PTYERR
-
3
ns
tPDMSS
simultaneous switching peak
propagation delay
CK and CK to output
[1][2] -
-
1.5
ns
tPHL
HIGH-to-LOW propagation delay
RESET to output
-
3
ns
Table 13.
Output edge rates
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
1
-
4
V/ns
dV/dt_f
falling edge slew rate
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
-
1
V/ns
相关PDF资料 |
PDF描述 |
|---|---|
| SSTUG32868ET/G | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176 |
| SSTUP32866EC/S | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTV16857EC | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| SSTV16859DGG,118 | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| SSTV16859BS,118 | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTUG32866 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G,518 | 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUG32866EC/G-T | 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUG32866EC/S | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
发布紧急采购，3分钟左右您将得到回复。