参数资料
| 型号： | ST16C554DCJ68-F |
| 厂商： | Exar Corporation |
| 文件页数： | 10/39页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B QUAD 68PLCC |
| 标准包装： | 19 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 16 字节 |
| 规程： | RS232 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC |
| 包装： | 管件 |
| 其它名称： | 1016-1265-5 |
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ST16C554/554D
18
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
4.4
Interrupt Status Register (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by THR empty (non-FIFO mode) or TX FIFO empty (FIFO mode).
MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or by writing to THR.
MSR interrupt is cleared by a read to the MSR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[5:4]: Reserved (Default 0)
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Empty)
5
0
MSR (Modem Status Register)
-
0
1
None (default)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C554DCJ68TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C554DCJ68TR-F | 功能描述:UART 接口集成电路 QUAD UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C554DCQ-0A-EB | 功能描述:界面开发工具 Supports C554D 64 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| ST16C554DCQ64 | 制造商:Exar Corporation 功能描述: |
| ST16C554DCQ64F | 制造商:Exar Corporation 功能描述: |
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