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参数资料
型号： ST16C554DCJ68-F
厂商： Exar Corporation
文件页数： 33/39页
文件大小： 0K
描述： IC UART FIFO 16B QUAD 68PLCC
标准包装： 19
特点： *
通道数： 4，QUART
FIFO's： 16 字节
规程： RS232
电源电压： 2.97 V ~ 5.5 V
带自动流量控制功能： 是
带故障启动位检测功能： 是
带调制解调器控制功能： 是
带CMOS： 是
安装类型： 表面贴装
封装/外壳： 68-LCC（J 形引线）
供应商设备封装： 68-PLCC
包装： 管件
其它名称： 1016-1265-5
ST16C554/554D
II
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 24
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 24
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 25
ABSOLUTE MAXIMUM RATINGS ................................................................................. 26
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 26
ELECTRICAL CHARACTERISTICS............................................................................... 26
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 26
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 27
TA = 0O TO +70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V, 70 PF LOAD WHERE
APPLICABLE
................................................................................................................................................ 27
FIGURE 11. CLOCK TIMING............................................................................................................................................................. 28
FIGURE 12. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 29
FIGURE 13. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D ................................................................................... 29
FIGURE 14. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 30
FIGURE 15. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 30
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 31
FIGURE 16. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 31
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 32
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 32
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 33
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D .............................. 33
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 34
PACKAGE DIMENSIONS................................................................................................................................ 35
REVISION HISTORY ..................................................................................................................................... 37
TABLE OF CONTENTS ..................................................................................................... I
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