参数资料
型号: ST6367B1/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封装: SHRINK, PLASTIC, DIP-42
文件页数: 11/84页
文件大小: 861K
代理商: ST6367B1/XXX
19/84
ST6365, ST6375, ST6385 ST6367, ST6377, ST6387
3.2 RESETS
The MCU can be reset in three ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
If RESET activation occurs in RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors if available.
When the level on the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors if
available. When the level of the RESET pin then
goes high, the initialization sequence is executed
following expiry of the internal delay period.
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se-
quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When the
power supply voltage rises to a sufficient level, the
oscillator starts to operate, whereupon an internal
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate-
ly following the internal delay.
The internal delay is generated by an on-chip
counter. The internal reset line is released 2048 in-
ternal clock cycles after release of the external re-
set.
The internal POR device is a static mechanism
which forces the reset state when VDD is below a
threshold voltage in the range 3.4 to 4.2 Volts (see
Figure 13). The circuit guarantees that the MCU
will exit or enter the reset state correctly, without
spurious effects, ensuring, for example, that EEP-
ROM contents are not corrupted.
Note: This feature is not available on OTP/EPROM
Devices.
Figure 13. Power ON/OFF Reset operation
Figure 14. Reset and Interrupt Processing
VR02037
VDD
4.2
3.4
t
V
t
POWER
ON/OFF
Threshold
DD
RESET
INT LATCH CLEARED
NMI MASK SET
RESET
( IF PRESENT )
SELECT
NMI MODE FLAGS
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTION
LOAD PC
VA000427
相关PDF资料
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