- 您现在的位置：买卖IC网 > PDF目录69373 > ST72F652AR4T1 (STMICROELECTRONICS) 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64 PDF资料下载
参数资料
| 型号： | ST72F652AR4T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, TQFP-64 |
| 文件页数： | 132/160页 |
| 文件大小： | 979K |
| 代理商： | ST72F652AR4T1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页当前第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页
ST7265x
73/160
USB INTERFACE (Cont’d)
Download Mode
IN transactions are managed the same way as in
normal mode (by software with the help of CTR in-
terrupt) but OUT transactions are managed by
hardware. This means that no CTR interrupt is
generated at the end of an OUT transaction and
the STAT_RX bits are set to valid by hardware
when the buffer is ready to receive new data. This
allows the 512-byte buffer to be written without
software intervention.
If the USB interface receives a packet which has a
length lower than the maximum packet size (writ-
ten in the CNT2RXR register, see Note below), the
USB interface switches back to normal mode and
generates a CTR interrupt and the STAT_RX bits
of the EP2R register are set to NAK by hardware
as in normal mode.
Upload Mode
OUT transactions are managed in the same way
as normal mode and IN transactions are managed
by hardware in the same way as OUT transactions
in download mode.
Bits 5:4 Reserved, forced by hardware to 0.
Bit 3 = CTR_RX
Reception Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after that the corresponding interrupt
has been serviced.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
USB INTERFACE (Cont’d)
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bits 1:0 = STAT_RX [1:0]
Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which is listed below:
Table 23. Reception Status Encoding
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
Note: These bits are write protected in download
mode (if MOD[1:0] =10b in the EP2RXR register)
ENDPOINT
2
TRANSMISSION
REGISTER
(EP2TXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 2
transmission. Bits 2:0 are also reset by a USB re-
set, either received from the USB or forced
through the FRES bit in the CTLR register.
Bit 3 = CTR_TX
Transmission Transfer Correct.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 2
1: Correct transfer in transmission on Endpoint 2
STAT_RX1 STAT_RX0
Meaning
00
DISABLED: reception trans-
fers cannot be executed.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled for reception.
70
0
000
CTR_T
X
DTOG
_TX
STA T_
TX1
STAT_
TX0
1
相关PDF资料 |
PDF描述 |
|---|---|
| ST72P651AR6T1/XXX | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64 |
| ST72T121J4B3S | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP42 |
| ST72T121J4B6S | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST72E121J4D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T121J4T6 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72P262M6/OZXTR | 制造商:STMicroelectronics 功能描述:ST72P262M6/OZXTR |
| ST72P324TA/OBZTR | 制造商:STMicroelectronics 功能描述: |
| ST72P324TA/OHXTR | 制造商:STMicroelectronics 功能描述: |
| ST72P4T128M-A05AU | 制造商:STEC Inc 功能描述:1GB,ECC,REG,DDR2-400,UNLEAD - Bulk |
| ST72T101G1B6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。