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参数资料
| 型号： | ST72T141K2MARE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO34 |
| 封装： | 0.300 INCH, LEAD FREE, PLASTIC, SOP-34 |
| 文件页数： | 87/131页 |
| 文件大小： | 3096K |
| 代理商： | ST72T141K2MARE |
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ST72141K2-Auto
59/131
MOTOR CONTROLLER (Cont’d)
8.1.4.3 PWM Manager
The PWM manager controls the motor via the six
output channels in voltage mode or current mode
depending on the V0C1 bit in the MCRA register.
A block diagram of this part is given in Figure 36.
Voltage Mode
In Voltage mode (V0C1 bit = ‘0’), the PWM is gen-
erated by the 16-bit A Timer.
Its duty cycle is programmed by software (refer to
Section 8.3 16-BIT TIMER) as required by the ap-
plication (speed regulation for example).
The current comparator is used for safety purpos-
es as a current limitation. For this feature, the de-
tected current must be present on the MCCFI pin
and the current limitation must be present on pin
OCP1A. This current limitation is fixed by a voltage
reference depending on the maximum current ac-
ceptable for the motor. This current limitation is
generated with the VDD voltage by means of an
external divider but can also be adjusted with an
external reference voltage (< 3.7 V). The external
components are adjusted by the user depending
on the application needs. In Voltage mode, it is
mandatory to set a current limitation.
In sensorless mode the BEMF zero crossing is
done during the PWM off time.
The PWM signal is directed to the channel manag-
er that connects it to the programmed outputs (see
Current Mode
In current mode, the PWM output signal is gener-
ated by a combination of the output of the meas-
urement window generator (see Figure 37) and
the output of the current comparator, and is direct-
ed to the output channel manager as well (Figure
The current reference is provided to the compara-
tor by the PWM output of the 16-bit Timer (0.25%
accuracy), filtered through a RC filter (external ca-
pacitor on pin OCP1A and an internal voltage di-
vider 30K and 70K).
The detected current input must be present on the
MCCFI pin.
To avoid spurious commutations due to parasitic
noise after switching on the PWM, a 2.5-s filter
can be applied on the comparator output by set-
ting the CFF bit in the MCRB register.
The On state of the resulting PWM starts at the
end of the measurement window (rising edge),
and ends either at the beginning of the next meas-
urement window (falling edge), or when the cur-
rent level is reached.
Figure 36. Current Feedback
MCCFI
2.5-s Filter
VCREF
R1
R2
16-bit Timer - PWM
OCP1A
CEXT
Common Mode = VDD - (1,4...1,0)V
VCREF MAX = VDD - 1,3 V
Power down mode
To Phase State
V0C1 bit
CFF bit
Sampling frequency
+
-
Control
MCRA Register
MCRA
(V)
R1ext
R2ext
VDD
(V)
(I)
Register
LEGEND:
(I): Current mode
(V): Voltage mode
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