ST7FLITE0
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7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components.
Main features
s
Clock Management
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 4 or 8
(enabled by option byte)
s
Reset Sequence Manager (RSM)
s
System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The ST7Flite0 contains an internal RC oscillator
with an accuracy of 1% for a given device, temper-
ature and voltage. It must be calibrated to obtain
the frequency required in the application. This is
done by software writing a calibration value in the
RCCR (RC Control Register).
Whenever the ST7FLITE0 microcontroller is reset,
the RCCR returns to its default value (FFh), i.e.
each time the device is reset, the calibration value
must be loaded in the RCCR. Predefined calibra-
tion values are stored in EEPROM for 3.0 and 5V
VDD supply voltages at 25°C, as shown in the fol-
lowing table.
Notes:
– See “ELECTRICAL CHARACTERISTICS” on
page 77. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability, it is recommended to
place a decoupling capacitor between the VDD
and VSS pins as close as possible to the ST7 de-
vice.
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these two bytes.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with VDD in
the 2.4V to 3.3V range
– The x8 PLL is intended for operation with VDD in
the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte descrip-
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then fOSC = 1MHz.
If both the RC oscillator and the PLL are disabled,
fOSC is driven by the external clock.
Figure 11. PLL Output Frequency Timing
Diagram
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACCPLL) is reached after
a stabilisation time of tSTAB (see Figure 11 and
13.3.5 Internal RC Oscillator and PLL)
Refer to section 7.5.4 on page 30 for a description
of the LOCKED bit in the SICSR register.
RCCR
Condition s
ST7FLITE09
Address
ST7FLIT E05
Address
RCCR0
VDD=5V
TA=25°C
fRC=1MHz
1000h and
FFDEh
RCCR1
VDD=3.0V
TA=25°C
fRC=700KHz
1001h and-
FFDFh
4/8 x
freq.
LOCKED bit set
tSTAB
tLOCK
input
t
Output
freq.
1